1. Field of the Invention
This invention relates to non-volatile flash memory cells in Multi-Level-Cell (MLC) operation, and more particularly, to a method of trimming threshold voltage of FET NVM cells in MLC operation.
2. Description of the Related Art
An Electrical-Erasable-Programmable Read Only Memory (EEPROM) cell is a semiconductor device having non volatile memory properties which can be electrically programmed and erased. EEPROM Non-Volatile Memory (NVM) cell comprises a Field Effect Transistor (FET) with a charge storing material to alter the threshold voltage of the FET. The non volatile memory properties enable the device to retain stored information once the power is turned off. The information is in the form of charges stored within the storing material (as shown in FIGS. 1A and 2A). Moreover, many kinds of EEPROM storage arts were developed (as shown in FIGS. 1B˜1E and FIGS. 2B˜2E). A “flash” EEPROM is an NVM device can be erased or programmed in a large number of memory cells in one program/erase operation.
Data is stored in a binary format in the NVM cell in a manner that the cell is set to a programmed state and reset to an erased state. Programming the cell is accomplished by storing charges in the storing material usually by means of tunneling or hot carrier injection. Erasing the cell is done by removing the charges from the storing material usually by means of tunneling.
In a single bit operation of an NVM cell, the erased state and programmed state can be assigned to binary code of “1” and “0”, respectively, or vice versa. The stored bit information of an NVM cell are represented by the threshold voltage levels of “programmed” and “erased” states of the NVM cell. In an N-bit operation of an NVM cell, 2N threshold voltage levels are required to represent the states of the N-bit binary code. For examples, 2-bit per cell operation requires 4 threshold voltage levels with one erased and three programmed; 4-bit per cell operation requires 16 threshold voltage levels with one erased and fifteen programmed, and so forth.
The goal of the MLC (Multi-Level Cell) storage is enabling multiple threshold voltage operation in single EEPROM cell. The threshold voltage of the NVM cell is altered depending on the amount of charges stored in the storing material. The basic techniques for accurate charge placement and sensing have the three major challenges for multi-bit storage identified:                Precise Charge Placement: The flash memory cell programming must be very accurately controlled, requiring a detailed understanding of the physics of programming as well as the control and timing of the voltages applied to the cell.        Precise Charge Sensing: The read operation of an MLC memory is basically an analog to digital conversion of the analog charge stored in the memory cell to digital data, a concept new to memory devices.        Stable Charge Storage: Meeting the data retention goals would require the stored charge to be stable with a leakage rate of less than one electron per day.        
A MLC is usually programmed to a desired threshold voltage level either by injecting certain amount of hot carriers or tunneling charges to the storing material. In programming a plurality of NVM cells in a memory array, the amounts of charges injected into the storing material in programming process vary with a range of distribution for a specific targeted threshold voltage level. The distribution is caused by different physical mechanisms such as the fluctuations of applied programming voltage biases and the non-uniformity of NVM cells from manufacturing process. The threshold voltage distribution of a plurality of NVM cells for a specific level imposes a limitation on the resolvability between threshold voltage levels. To reduce the distribution, a programming-verification process for the lower bound threshold voltage is introduced in the conventional way of programming MLC operation. The threshold voltages of a plurality of NVM cells are repeatedly programmed and verified until the entire targeted NVM cells are above the lower bound threshold voltage for a specific threshold voltage level. However, since there is no high bound threshold voltage limitations for the specific threshold voltage level the over-programmed cells for the level may be higher than the lower bound threshold voltage of its higher neighboring level resulting in misreading the stored bit information. To prevent the undesirable misreading in MLC operation, the separation of threshold levels must increase to a larger margin resulting in the number reduction of threshold voltage levels in an available threshold voltage range.
In order to divide more threshold levels and to meet the reading resolvability for storing more bits in a single cell, an upper bound threshold voltage is set to limit the threshold voltages of over-programmed NVM cells. The threshold voltages of a plurality of NVM cells for a specific threshold voltage level are adjusted to be within the band of the lower and upper bound threshold voltages as shown in FIG. 3 for an example of 4-bit MCL operation. Li and Hi represent the lower bound and the high bound threshold voltages, respectively for the threshold voltage level i; Si are the applied voltages to the NVM control gate for i=0, . . . , 14, for probing the 16 threshold voltage levels. It is known that when a voltage applied to the control gate voltage of an NVM cell is above its threshold voltage the NVM cell will be turned on. As illustrated in FIG. 3 when the applied control gate voltages change from Si-1 to Si the NVM cells with threshold voltages within the band of the level i will be turned from “off” state to ““on” state. Therefore, the transition of NVM off-on process can be used as a digital signature of the storing information represented by 4 digital bits (24=16 levels of distinctive threshold voltage bands).
To program and to trim a plurality of NVM threshold voltages to the threshold voltage band for a level i require programming and trimming methods to NVM cells. The conventional programming methods, either tunneling or hot carrier injection, tend to increase the threshold voltages of NVM cells with increasing number of programming pulse shots. The threshold voltage increments also become smaller and smaller as the number of pulse shots increases. The conventional programming methods are sufficient for the lower bound threshold voltage adjustment. However, since the over-programmed NVM cells require to be trimmed down within the threshold voltage band of a specific level i, the trimming threshold voltage increments must be smaller than the threshold voltage band width of the level to prevent over-trimmed NVM threshold voltages below the lower bound of the threshold voltage band.
To lower the threshold voltages of programmed NVM cells is done by removing the stored charges from the storing materials. The conventional way of removing the stored charges is either by tunneling out the stored charges or by injecting hot carriers with opposite charge. However, those processes down-shift the programmed NVM threshold voltages too far lower threshold voltages from the programmed states. Usually, the threshold voltages reach the erased state after several conventional erasing shots. The conventional charge removing process is not able to trim down the threshold voltages of programmed NVM cells with a sufficient small threshold voltage increment. In this disclosure, we provide threshold voltage trimming methods to trim down the threshold voltages of a plurality of programmed NVM cells with small threshold voltage increments. The down-shifted threshold voltage increment can be adjusted to be small enough such that the threshold voltages of a plurality of NVM cells guarantee to be within the desired threshold voltage band for a specific level in MLC operation.